Dubbed Sierra Forest and Granite Rapids, Intel’s forthcoming Xeon chips are set to introduce innovative core architectures and place a spotlight on memory and I/O enhancements. Intel showcased these upcoming Xeon chips, named Sierra Forest and Granite Rapids, during the Hot Chips 2023 event. These chips stand out as the inaugural Xeon batch that will integrate the newly conceived Efficient-core (E-core) technology alongside the existing Performance-core (P-core) model.
In terms of robustness, these chips are expected to surpass their predecessor, known as Sapphire Rapids, by providing up to 144 cores, addressing the demand for higher memory and I/O throughput. This improvement is crucial for Intel to rival AMD’s Epyc series.
According to Intel, their Sierra Forest chips, powered by E-cores, are projected to achieve 2.5 times better rack space utilization and a 2.4 times surge in energy efficiency over Sapphire Rapids. Meanwhile, Granite Rapids chips, driven by P-cores, are expected to deliver two to threefold augmented performance for blended AI operations. Intel ties this significant boost to a 2.8x enhancement in memory bandwidth.
To elaborate, P-core is tailored for peak computational demands, while the E-core is designed for lighter, less demanding computational activities. As not all tech processes necessitate powerful CPUs, deploying a P-core for basic operations like file handling would be excessive. On the contrary, E-core is energy-efficient.
A distinct feature of Sierra Forest and Granite Rapids is their chiplet-based structure, diverging from the conventional single silicon layout. This permits Intel to flexibly combine P-core and E-core architectures for bespoke chip solutions.
Positioning Granite Rapids as a successor to Sapphire Rapids in the conventional Xeon server processor line, each P-core will be equipped with 2MB of L2 cache and 4MB of L3. While Intel remains tight-lipped about the exact core numbers for Granite Rapids, they confirmed its compatibility with up to eight sockets within one server.
Intel’s P-core architecture will incorporate what is termed as Advanced Matrix Extensions (AMX) to bolster deep learning tasks, complete with FP16 acceleration, a mainstream protocol for AI processes.
Sierra Forest’s E-cores are strategized to rival Arm chips from entities like Ampere and Fujitsu. Here, Intel disclosed a maximum of 144 cores, fine-tuned for power conservation. Tailored for single or dual-socket configurations, Sierra Forest will have an approximate TDP of 200W, regarded as energy-saving in modern terms.
Additionally, Sierra Forest chips will house advanced memory controllers, accommodating 12 channels (an upgrade from Sapphire Rapids’ eight channels) of DDR5-6400 memory alongside 136 lanes of PCIe 5.0 / CXL 2.0 connectivity. Along with DDR memory compatibility, these fifth-gen Xeon chips will be in sync with Intel’s newly engineered MCR memory, ensuring a 30%-40% surge in memory bandwidth compared to conventional DIMMs.
These fifth-gen Xeon chips are slated for launch the following year.
Hot Chips, a revered yearly gathering, provides an intensive exploration of electrical engineering nuances. Hosted every August at Stanford University, a breeding ground for numerous iconic chip innovators like Intel’s Pat Gelsinger and Nvidia’s Jensen Huang, it remains a significant event in the chip design landscape.